Radio frequency integrated circuit (RFIC) and monolithic microwave integrated circuit (MIMIC) technology provides the core components for many microwave and millimeter-wave (mmWave) communication, radar, and sensing systems. The transmit/receive module of a mobile communication or a phased-array radar system in the form of a single MIMIC is often most sought after for designers. Massive multiple-input/multiple-output (MIMO) technology utilizing hundreds of antenna elements has drawn attention as a key antenna configuration for beamforming applications. Realizing the massive MIMO concept of active phased-array antennas will require small-size, low-power-consumption, and highly accurate phase control over the wide-band frequency range, which poses significant challenges for the RF front end. The MIMIC compatibility which provides the solution to reduce the parasitic elements for operating efficiently at high frequencies is a must for a compact RF front end module. Accordingly, strong demand has arisen for a monolithic semiconductor integrated circuit in which high-speed field effect transistors (FETs), PIN diodes, and Schottky diodes form on a single chip. These microwave diodes can be incorporated into circuits of multiple functions, such as switches, limiters, mixers, phase shifters, attenuators, modulators, detectors, electrostatic protectors, etc. Moreover, monolithically integrating FETs and diodes on the same chip can essentially eliminate additional transition losses.
FIG. 5 discloses a conventional integrated circuit device that includes a PIN photodiode 90 that is monolithically integrated with a high electron mobility transistor (HEMT) 91 that is monolithically integrated with a heterojunction bipolar transistor (HBT) 92 on an InP substrate 901 in a multi-layer structure. The PIN photodiode 90 comprises a PIN photodiode epitaxial structure mesa 93, a first electrode 912, and a second electrode 911. The HEMT 91 comprises a HEMT epitaxial structure mesa 94, a gate electrode 914, a source electrode 913, and a drain electrode 915. The HBT 92 comprises a HBT epitaxial structure mesa 95, a collector electrode 918, a base electrode 917, and an emitter electrode 916. Fabricating the structure of the embodiment FIG. 5 needs the following steps: (1) forming an n-type doped GaInAs (n-GaInAs) layer 902 on an InP substrate 901; (2) forming an intrinsic GaInAs (i-GaInAs) layer 903 on the n-GaInAs layer 902; (3) forming a p-type doped GaInAs (p-GaInAs) layer 904 on the i-GaInAs layer 903; (4) defining the respective etching areas (not shown) of the p-GaInAs layer 904, the i-GaInAs layer 903, and the n-GaInAs layer 902; and etching sequentially the p-GaInAs layer 904, i-GaInAs layer 903, and n-GaInAs layer 902, forming a PIN photodiode epitaxial structure mesa 93 shown in FIG. 5; (5) forming a selective growth mask (not shown) on the PIN photodiode epitaxial structure mesa 93 and the InP substrate 901; (6) removing the selective growth mask (except the selective growth mask covering the PIN photodiode epitaxial structure mesa 93; not shown) such that the InP substrate 901 is exposed; (7) forming an i-GaInAs layer 905 on the exposed InP substrate 901; (8) forming an n-AlInAs layer 906 on the i-GaInAs layer 905; (9) defining the respective etching areas (not shown) of the n-AlInAs layer 906 and the i-GaInAs layer 905; and etching sequentially the n-AlInAs layer 906 and i-GaInAs layer 905, forming a HEMT epitaxial structure mesa 94 shown in FIG. 5; (10) forming a selective growth mask (not shown) on the PIN photodiode epitaxial structure mesa 93, the HEMT epitaxial structure mesa 94, and the InP substrate 901; (11) removing the selective growth mask (except the selective growth mask covering the PIN photodiode epitaxial structure mesa 93 and the HEMT epitaxial structure mesa 94; not shown) such that the InP substrate 901 is exposed; (12) forming an n+-type doped GaInAs (n+-GaInAs) layer 907 on the exposed InP substrate 901; (13) forming an n-GaInAs layer 908 on the n+-GaInAs layer 907; (14) forming a p-GaInAs layer 909 on the n-GaInAs layer 908; (15) forming an n-type doped InP (n-InP) layer 910 on the p-GaInAs layer 909; (16) defining the respective etching areas (not shown) of the n-InP layer 910, the p-GaInAs layer 909, the n-GaInAs layer 908, and the n+-GaInAs layer 907; and etching sequentially the n-InP layer 910, p-GaInAs layer 909, n-GaInAs layer 908, and n+-GaInAs layer 907, forming a HBT epitaxial structure mesa 95 shown in FIG. 5; (17) removing the selective growth mask covering the PIN photodiode epitaxial structure mesa 93 and the HEMT epitaxial structure mesa 94 (not shown); (18) forming a first electrode 912 and a second electrode 911 on the n-GaInAs layer 902 and the p-GaInAs layer 904, respectively, completing a PIN photodiode 90; (19) forming a source electrode 913 and a drain electrode 915 on the n-AlInAs layer 906; and forming a gate electrode 914 on the n-AlInAs layer 906 between the source electrode 913 and the drain electrode 915, completing a HEMT 91; and (20) forming a collector electrode 918, a base electrode 917, and an emitter electrode 916 on the n+-GaInAs layer 907, the p-GaInAs layer 909, and the n-InP layer 910, respectively, completing a HBT 92. Demonstrations of III-V compound semiconductor monolithically integrated circuit device with transistors and diodes reported in the prior art shown in FIG. 5 employ complex processes involving multiple epitaxial growths and regrowths. This regrowth of material requires additional processing steps and sophisticated cleaning procedures that lead to low yield and high cost fabrication. As a result, the aforementioned epitaxial layer regrowing process is problematic and unsatisfactory for mass production of mmWave communication, radar, and sensing systems.
Accordingly, a new approach to achieving a monolithically integrated circuit device with transistors and diodes is desirable.